9 files changed, 336 insertions(+), 14 deletions(-)

M StartJLinkServer.sh
M Target_RT1051.cmake
M board/rt1051/crashdump/crashcatcher_impl.cpp
R board/rt1051/ldscripts/{memory => memory_T6}.ld
A board/rt1051/ldscripts/memory_T7.ld
M cmake/modules/ProjectConfig.cmake
M evkbimxrt1050_sdram_init.jlinkscript
A evkbimxrt1050_sdram_init_T6.jlinkscript
M module-bsp/board/rt1051/common/board.cpp

@@ 1,8 1,9 @@
 #!/usr/bin/env bash
-# Copyright (c) 2017-2020, Mudita Sp. z.o.o. All rights reserved.
+# Copyright (c) 2017-2021, Mudita Sp. z.o.o. All rights reserved.
 # For licensing, see https://github.com/mudita/MuditaOS/LICENSE.md
 
 declare -A OPTS=( ['continous']=' -singlerun ' ['verify']='  ' ['speed']=' -speed 25000 ')
+jlinkScriptFileName="evkbimxrt1050_sdram_init.jlinkscript"
 
 help()
 {


@@ 13,6 14,7 @@ Params:
     continous   - run in continous mode
     verify      - verify data loaded
     speed       - change speed (please mind 30000 is max by docs)
+    T6          - run for the T6 board 
 EOF
 }
 while [[ $# -gt 0 ]]; do


@@ 28,6 30,10 @@ while [[ $# -gt 0 ]]; do
             OPTS[$1]=" -speed $2 "
             shift
             ;;
+        "T6")
+            echo "run for the T6 board"
+            jlinkScriptFileName="evkbimxrt1050_sdram_init_T6.jlinkscript"
+            ;;
         *)
             help
             ;;


@@ 35,7 41,7 @@ while [[ $# -gt 0 ]]; do
     shift
 done
 CMD="JLinkGDBServerCLExe -if SWD -device MCIMXRT1051                     \
-    -jlinkscriptfile evkbimxrt1050_sdram_init.jlinkscript -strict -ir    \
+    -jlinkscriptfile $jlinkScriptFileName -strict -ir    \
     -rtos GDBServer/RTOSPlugin_FreeRTOS                                  \
     ${OPTS[@]}"
 

@@ 110,5 110,4 @@ SET(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
 
 
 
-set(CMAKE_EXE_LINKER_FLAGS "-nostdlib -Xlinker --gc-sections -Xlinker --sort-section=alignment -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -Xlinker -print-memory-usage -T ${LDSCRIPTSDIR}/libs.ld -T ${LDSCRIPTSDIR}/memory.ld -T ${LDSCRIPTSDIR}/sections.ld -nostartfiles" CACHE INTERNAL "")
 SET(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY BOTH)

@@ 17,9 17,13 @@ const CrashCatcherMemoryRegion *CrashCatcher_GetMemoryRegions(void)
         {0x20200000, 0x20210000, CRASH_CATCHER_BYTE},
         // SRAM_DTC
         {0x20000000, 0x20070000, CRASH_CATCHER_BYTE},
-        // intentionally skip text section
-        // BOARD_SDRAM_HEAP
+    // intentionally skip text section
+    // BOARD_SDRAM_HEAP
+#if defined(PURE_SDRAM_64_MB) && (PURE_SDRAM_64_MB == 1)
+        {0x80620000, 0x84000000, CRASH_CATCHER_BYTE},
+#else
         {0x80620000, 0x81000000, CRASH_CATCHER_BYTE},
+#endif
         // end tag
         {0xFFFFFFFF, 0xFFFFFFFF, CRASH_CATCHER_BYTE},
     };

@@ 0,0 1,25 @@
+/*
+ * (c) Code Red Technologies Ltd, 2008-2013
+ * (c) NXP Semiconductors 2013-2018
+ * Generated linker script file for MIMXRT1052xxxxB
+ * Created from memory.ldt by FMCreateLinkMemory
+ * Using Freemarker v2.3.23
+ * MCUXpresso IDE v10.2.0 [Build 759] [2018-05-15]  on 2018-07-30 10:43:20
+ *
+ * Modified by Mudita
+ */
+MEMORY
+{
+        /********************************   WARNING   *******************************/
+        /*                                                                          */
+        /* must be kept in sync with 'board/rt1051/crashdump/crashcatcher_impl.cpp' */
+        /*                                                                          */
+        /****************************************************************************/
+
+	/* Define each memory region */
+	SRAM_OC (rwx) : ORIGIN = 0x20200000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */
+	/*SRAM_ITC (rwx) : ORIGIN = 0x0, LENGTH = 0x0*/ /* 0K bytes (alias RAM2) */
+	SRAM_DTC (rwx) : ORIGIN = 0x20000000, LENGTH = 0x70000 /* 448K bytes (alias RAM3) */
+	BOARD_SDRAM_TEXT (rx) : ORIGIN = 0x80000000, LENGTH = 0x2000000 /* 32 MB for application code */
+	BOARD_SDRAM_HEAP (rwx) : ORIGIN = 0x82000000, LENGTH = 0x2000000 /* 32 MB for heap (alias RAM4) */
+}

@@ 49,6 49,19 @@ else()
     set (USB_DEVICE_PRODUCT_ID 0x0622 CACHE INTERNAL "Sets USB_DEVICE_PRODUCT_ID to Windows MTP Simulator Product ID")
 endif()
 
+option(PURE_HW_TARGET "PURE_HW_TARGET" T7)
+if (${PURE_HW_TARGET} STREQUAL "T6")
+    message("Building for T6")
+    set (MEMORY_LINKER_FILE "memory_T6.ld")
+    set (PROJECT_CONFIG_USER_DYNMEM_SIZE 9*1024*1024 CACHE INTERNAL "")
+    set (PURE_SDRAM_64_MB 0 CACHE INTERNAL "")
+else()
+    message("Building for T7 - 64MB SDRAM !")
+    set (MEMORY_LINKER_FILE "memory_T7.ld")
+    set (PROJECT_CONFIG_USER_DYNMEM_SIZE 28*1024*1024 CACHE INTERNAL "")
+    set (PURE_SDRAM_64_MB 1 CACHE INTERNAL "")
+endif()
+
 #Config options described in README.md
 set(PROJECT_CONFIG_DEFINITIONS
         LOG_USE_COLOR=${LOG_USE_COLOR}


@@ 57,7 70,8 @@ set(PROJECT_CONFIG_DEFINITIONS
         SYSTEM_VIEW_ENABLED=${SYSTEM_VIEW_ENABLED}
         USBCDC_ECHO_ENABLED=${USBCDC_ECHO_ENABLED}
         LOG_LUART_ENABLED=${LOG_LUART_ENABLED}
-        PROJECT_CONFIG_USER_DYNMEM_SIZE=9*1024*1024
+        PROJECT_CONFIG_USER_DYNMEM_SIZE=${PROJECT_CONFIG_USER_DYNMEM_SIZE}
+        PURE_SDRAM_64_MB=${PURE_SDRAM_64_MB}
         USB_DEVICE_VENDOR_ID=${USB_DEVICE_VENDOR_ID}
         USB_DEVICE_PRODUCT_ID=${USB_DEVICE_PRODUCT_ID}
         MAGIC_ENUM_RANGE_MAX=256


@@ 66,3 80,7 @@ set(PROJECT_CONFIG_DEFINITIONS
 
 message(STATUS "BlueKitchen selected")
 set(BT_STACK "BlueKitchen")
+
+if(${PROJECT_TARGET} STREQUAL "TARGET_RT1051")
+set(CMAKE_EXE_LINKER_FLAGS "-nostdlib -Xlinker --gc-sections -Xlinker --sort-section=alignment -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -Xlinker -print-memory-usage -T ${LDSCRIPTSDIR}/libs.ld -T ${LDSCRIPTSDIR}/${MEMORY_LINKER_FILE} -T ${LDSCRIPTSDIR}/sections.ld -nostartfiles" CACHE INTERNAL "")
+endif()

@@ 136,6 136,8 @@ void SDRAM_Init() {
   MEM_WriteU32(0x401F80A8,0x00000000); // EMC_37
   MEM_WriteU32(0x401F80AC,0x00000000); // EMC_38
   MEM_WriteU32(0x401F80B0,0x00000010); // EMC_39
+  MEM_WriteU32(0x401F80B4,0x00000000); // EMC_40
+  MEM_WriteU32(0x401F80B8,0x00000000); // EMC_41
   
   // PAD ctrl
   // drive strength = 0x7 to increase drive strength


@@ 180,16 182,18 @@ void SDRAM_Init() {
   MEM_WriteU32(0x401F8298,0x000110F9); // EMC_37
   MEM_WriteU32(0x401F829C,0x000110F9); // EMC_38
   MEM_WriteU32(0x401F82A0,0x000110F9); // EMC_39
+  MEM_WriteU32(0x401F82A4,0x000110F9); // EMC_40
+  MEM_WriteU32(0x401F82A8,0x000110F9); // EMC_41
 
   // Config SDR Controller Registers/
   MEM_WriteU32(0x402F0000,0x10000004); // MCR
-  MEM_WriteU32(0x402F0008,0x00030524); // BMCR0
-  MEM_WriteU32(0x402F000C,0x06030524); // BMCR1
-  MEM_WriteU32(0x402F0010,0x80000019); // BR0, 16MB OK
-  MEM_WriteU32(0x402F0040,0x00000F31); // SDRAMCR0 OK
-  MEM_WriteU32(0x402F0044,0x00652922); // SDRAMCR1
-  MEM_WriteU32(0x402F0048,0x000a0b0d); // SDRAMCR2
-  MEM_WriteU32(0x402F004C,0x0f0f0a00); // SDRAMCR3
+  MEM_WriteU32(0x402F0008,0x20200E44); // BMCR0
+  MEM_WriteU32(0x402F000C,0x20200E40); // BMCR1
+  MEM_WriteU32(0x402F0010,0x8000001D); // BR0, 64MB OK
+  MEM_WriteU32(0x402F0040,0x00000E31); // SDRAMCR0 OK
+  MEM_WriteU32(0x402F0044,0x00774D22); // SDRAMCR1
+  MEM_WriteU32(0x402F0048,0x000A0B0D); // SDRAMCR2
+  MEM_WriteU32(0x402F004C,0x09090801); // SDRAMCR3
   MEM_WriteU32(0x402F0090,0x80000000); // IPCR0 OK
   MEM_WriteU32(0x402F0094,0x00000002); // IPCR1 OK
   MEM_WriteU32(0x402F0098,0x00000000); // IPCR2 OK

@@ 0,0 1,258 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ 
+void Load_Dcdc_Trim()
+{
+  unsigned int ocotp_base;  
+  unsigned int dcdc_base;  
+  unsigned int ocotp_fuse_bank0_base;  
+  unsigned int reg;
+  unsigned int index;
+  unsigned int trim_value;
+  unsigned int dcdc_trim_loaded;
+  ocotp_base = 0x401F4000;
+  ocotp_fuse_bank0_base = 0x401F4000 + 0x400;
+  dcdc_base = 0x40080000;
+  dcdc_trim_loaded = 0;
+  reg = MEM_ReadU32(ocotp_fuse_bank0_base + 0x90);
+  if (reg & (1<<10))
+  {
+      trim_value = (reg & (0x1F << 11)) >> 11;
+      reg = (MEM_ReadU32(dcdc_base + 0x4) & ~(0x1F << 24)) | (trim_value << 24);
+      MEM_WriteU32(dcdc_base + 0x4, reg);
+      dcdc_trim_loaded = 1;
+  }
+  // DCDC_VOLT_CHANG_EN
+  reg = MEM_ReadU32(ocotp_fuse_bank0_base + 0x80);
+  if (reg & (1<<30))
+  {
+    index = (reg & (3 << 28)) >> 28;
+    if (index < 4)
+    {
+      reg = (MEM_ReadU32(dcdc_base + 0xC) & ~(0x1F)) | (0xF + index);
+      MEM_WriteU32(dcdc_base + 0xC, reg);
+      dcdc_trim_loaded = 1;
+    }
+  }
+  if (dcdc_trim_loaded)
+  {
+      // delay 1ms for dcdc to get stable
+      SYS_Sleep(1);
+      JLINK_SYS_Report("DCDC trim value loaded.");
+  }
+}
+ 
+void Clock_Init() 
+{
+    //
+  MEM_WriteU32(0x400FC068,0xffffffff);
+  MEM_WriteU32(0x400FC06C,0xffffffff);
+
+  MEM_WriteU32(0x400FC070,0xffffffff);
+  MEM_WriteU32(0x400FC074,0xffffffff);
+  MEM_WriteU32(0x400FC078,0xffffffff);
+  MEM_WriteU32(0x400FC07C,0xffffffff);
+  MEM_WriteU32(0x400FC080,0xffffffff);
+  MEM_WriteU32(0x400D8030,0x00002001); // CCM_ANALOG_PLL_SYS
+  MEM_WriteU32(0x400D8100,0x001d0000);  // CCM_ANALOG_PFD_528
+  MEM_WriteU32(0x400FC014,0x00010D40); // CCM_CBCDR
+  JLINK_SYS_Report("Clock Init Done");
+}
+void SDRAM_WaitIpCmdDone(void) 
+{
+  unsigned int reg;
+  do
+  {
+      reg = MEM_ReadU32(0x402F003C);
+  }while((reg & 0x3) == 0);
+  
+  MEM_WriteU32(0x402F003C,0x00000003); // clear IPCMDERR and IPCMDDONE bits
+}
+void SDRAM_Init() {
+  // Config IOMUX for SDRAM
+  MEM_WriteU32(0x401F8014,0x00000000); // EMC_00
+  MEM_WriteU32(0x401F8018,0x00000000); // EMC_01
+  MEM_WriteU32(0x401F801C,0x00000000); // EMC_02
+  MEM_WriteU32(0x401F8020,0x00000000); // EMC_03
+  MEM_WriteU32(0x401F8024,0x00000000); // EMC_04
+  MEM_WriteU32(0x401F8028,0x00000000); // EMC_05
+  MEM_WriteU32(0x401F802C,0x00000000); // EMC_06
+  MEM_WriteU32(0x401F8030,0x00000000); // EMC_07
+  MEM_WriteU32(0x401F8034,0x00000000); // EMC_08
+  MEM_WriteU32(0x401F8038,0x00000000); // EMC_09
+  MEM_WriteU32(0x401F803C,0x00000000); // EMC_10
+  MEM_WriteU32(0x401F8040,0x00000000); // EMC_11
+  MEM_WriteU32(0x401F8044,0x00000000); // EMC_12
+  MEM_WriteU32(0x401F8048,0x00000000); // EMC_13
+  MEM_WriteU32(0x401F804C,0x00000000); // EMC_14
+  MEM_WriteU32(0x401F8050,0x00000000); // EMC_15
+  MEM_WriteU32(0x401F8054,0x00000000); // EMC_16
+  MEM_WriteU32(0x401F8058,0x00000000); // EMC_17
+  MEM_WriteU32(0x401F805C,0x00000000); // EMC_18
+  MEM_WriteU32(0x401F8060,0x00000000); // EMC_19
+  MEM_WriteU32(0x401F8064,0x00000000); // EMC_20
+  MEM_WriteU32(0x401F8068,0x00000000); // EMC_21
+  MEM_WriteU32(0x401F806C,0x00000000); // EMC_22
+  MEM_WriteU32(0x401F8070,0x00000000); // EMC_23
+  MEM_WriteU32(0x401F8074,0x00000000); // EMC_24
+  MEM_WriteU32(0x401F8078,0x00000000); // EMC_25
+  MEM_WriteU32(0x401F807C,0x00000000); // EMC_26
+  MEM_WriteU32(0x401F8080,0x00000000); // EMC_27
+  MEM_WriteU32(0x401F8084,0x00000000); // EMC_28
+  MEM_WriteU32(0x401F8088,0x00000000); // EMC_29
+  MEM_WriteU32(0x401F808C,0x00000000); // EMC_30
+  MEM_WriteU32(0x401F8090,0x00000000); // EMC_31
+  MEM_WriteU32(0x401F8094,0x00000000); // EMC_32
+  MEM_WriteU32(0x401F8098,0x00000000); // EMC_33
+  MEM_WriteU32(0x401F809C,0x00000000); // EMC_34
+  MEM_WriteU32(0x401F80A0,0x00000000); // EMC_35
+  MEM_WriteU32(0x401F80A4,0x00000000); // EMC_36
+  MEM_WriteU32(0x401F80A8,0x00000000); // EMC_37
+  MEM_WriteU32(0x401F80AC,0x00000000); // EMC_38
+  MEM_WriteU32(0x401F80B0,0x00000010); // EMC_39
+  
+  // PAD ctrl
+  // drive strength = 0x7 to increase drive strength
+  // otherwise the data7 bit may fail.
+  MEM_WriteU32(0x401F8204,0x000110F9); // EMC_00
+  MEM_WriteU32(0x401F8208,0x000110F9); // EMC_01
+  MEM_WriteU32(0x401F820C,0x000110F9); // EMC_02
+  MEM_WriteU32(0x401F8210,0x000110F9); // EMC_03
+  MEM_WriteU32(0x401F8214,0x000110F9); // EMC_04
+  MEM_WriteU32(0x401F8218,0x000110F9); // EMC_05
+  MEM_WriteU32(0x401F821C,0x000110F9); // EMC_06
+  MEM_WriteU32(0x401F8220,0x000110F9); // EMC_07
+  MEM_WriteU32(0x401F8224,0x000110F9); // EMC_08
+  MEM_WriteU32(0x401F8228,0x000110F9); // EMC_09
+  MEM_WriteU32(0x401F822C,0x000110F9); // EMC_10
+  MEM_WriteU32(0x401F8230,0x000110F9); // EMC_11
+  MEM_WriteU32(0x401F8234,0x000110F9); // EMC_12
+  MEM_WriteU32(0x401F8238,0x000110F9); // EMC_13
+  MEM_WriteU32(0x401F823C,0x000110F9); // EMC_14
+  MEM_WriteU32(0x401F8240,0x000110F9); // EMC_15
+  MEM_WriteU32(0x401F8244,0x000110F9); // EMC_16
+  MEM_WriteU32(0x401F8248,0x000110F9); // EMC_17
+  MEM_WriteU32(0x401F824C,0x000110F9); // EMC_18
+  MEM_WriteU32(0x401F8250,0x000110F9); // EMC_19
+  MEM_WriteU32(0x401F8254,0x000110F9); // EMC_20
+  MEM_WriteU32(0x401F8258,0x000110F9); // EMC_21
+  MEM_WriteU32(0x401F825C,0x000110F9); // EMC_22
+  MEM_WriteU32(0x401F8260,0x000110F9); // EMC_23
+  MEM_WriteU32(0x401F8264,0x000110F9); // EMC_24
+  MEM_WriteU32(0x401F8268,0x000110F9); // EMC_25
+  MEM_WriteU32(0x401F826C,0x000110F9); // EMC_26
+  MEM_WriteU32(0x401F8270,0x000110F9); // EMC_27
+  MEM_WriteU32(0x401F8274,0x000110F9); // EMC_28
+  MEM_WriteU32(0x401F8278,0x000110F9); // EMC_29
+  MEM_WriteU32(0x401F827C,0x000110F9); // EMC_30
+  MEM_WriteU32(0x401F8280,0x000110F9); // EMC_31
+  MEM_WriteU32(0x401F8284,0x000110F9); // EMC_32
+  MEM_WriteU32(0x401F8288,0x000110F9); // EMC_33
+  MEM_WriteU32(0x401F828C,0x000110F9); // EMC_34
+  MEM_WriteU32(0x401F8290,0x000110F9); // EMC_35
+  MEM_WriteU32(0x401F8294,0x000110F9); // EMC_36
+  MEM_WriteU32(0x401F8298,0x000110F9); // EMC_37
+  MEM_WriteU32(0x401F829C,0x000110F9); // EMC_38
+  MEM_WriteU32(0x401F82A0,0x000110F9); // EMC_39
+
+  // Config SDR Controller Registers/
+  MEM_WriteU32(0x402F0000,0x10000004); // MCR
+  MEM_WriteU32(0x402F0008,0x00030524); // BMCR0
+  MEM_WriteU32(0x402F000C,0x06030524); // BMCR1
+  MEM_WriteU32(0x402F0010,0x80000019); // BR0, 16MB OK
+  MEM_WriteU32(0x402F0040,0x00000F31); // SDRAMCR0 OK
+  MEM_WriteU32(0x402F0044,0x00652922); // SDRAMCR1
+  MEM_WriteU32(0x402F0048,0x000a0b0d); // SDRAMCR2
+  MEM_WriteU32(0x402F004C,0x0f0f0a00); // SDRAMCR3
+  MEM_WriteU32(0x402F0090,0x80000000); // IPCR0 OK
+  MEM_WriteU32(0x402F0094,0x00000002); // IPCR1 OK
+  MEM_WriteU32(0x402F0098,0x00000000); // IPCR2 OK
+  MEM_WriteU32(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
+  SDRAM_WaitIpCmdDone();
+  MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
+  SDRAM_WaitIpCmdDone();
+  MEM_WriteU32(0x402F009C,0xA55A000C); // SD_CC_IAF
+  SDRAM_WaitIpCmdDone();
+  MEM_WriteU32(0x402F00A0,0x00000033); // IPTXDAT OK
+  MEM_WriteU32(0x402F009C,0xA55A000A); // SD_CC_IMS
+  SDRAM_WaitIpCmdDone();
+  MEM_WriteU32(0x402F004C,0x08080A01 ); // enable sdram self refresh again after initialization done.
+
+  JLINK_SYS_Report("SDRAM Init Done");
+}
+void INTRAM_Init() {
+    unsigned int gpr14_addr;
+    unsigned int gpr16_addr;
+    unsigned int gpr17_addr;
+    unsigned int ret;
+    
+    gpr14_addr = 0x400AC038;
+    gpr16_addr = 0x400AC040;
+    gpr17_addr = 0x400AC044;
+    ret = 0;
+    
+    // 448 KBytes of DTCM
+    MEM_WriteU32(gpr17_addr,0x5AAAAAAA);
+    
+    
+    ret = MEM_ReadU32(gpr16_addr);
+    
+    // Turn off DTCM
+    //ret &= ~0x02;
+    // Turn off ITCM
+    ret &= ~0x01;
+    MEM_WriteU32(gpr16_addr,ret);
+    
+    
+    // Configure DTCM/ITCM size
+    ret = MEM_ReadU32(gpr14_addr);
+    // Mask ITCM/DTCM size bits
+    ret &= ~0xFF0000;
+    // Set DTCM size to 512KBytes
+    ret |= 0xA00000;
+    MEM_WriteU32(gpr14_addr,ret);
+    
+    ret = MEM_ReadU32(gpr16_addr);
+    
+    // FlexRAM_BANK_CFG_SEL
+    ret &= ~0x04;
+    ret |= 0x04;
+    MEM_WriteU32(gpr16_addr,ret);
+    JLINK_SYS_Report("INTRAM Init Done");
+}
+/* SetupTarget */
+int AfterResetTarget(void) {
+  JLINK_SYS_Report("Enabling i.MXRT SDRAM");
+  /*Load_Dcdc_Trim();*/
+  Clock_Init();
+  SDRAM_Init();
+  INTRAM_Init();
+  JLINK_SYS_Report("Enable Power Switch On for debug");
+  MEM_WriteU32(0x401BC000, 128);
+}

@@ 155,7 155,11 @@ namespace bsp
          * BOARD_SDRAM_TEXT
          */
         MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
+#if defined(PURE_SDRAM_64_MB) && (PURE_SDRAM_64_MB == 1)
+        MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
+#else
         MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
+#endif
 
         /* The define sets the cacheable memory to shareable,
          * this suggestion is referred from chapter 2.2.1 Memory regions,


@@ 169,8 173,12 @@ namespace bsp
          * BOARD_SDRAM_HEAP
          */
         MPU->RBAR = ARM_MPU_RBAR(9, reinterpret_cast<std::uintptr_t>(__sdram_cached_start));
+#if defined(PURE_SDRAM_64_MB) && (PURE_SDRAM_64_MB == 1)
+        MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
+#else
         MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
-#endif
+#endif // PURE_SDRAM_64_MB
+#endif // SDRAM_IS_SHAREABLE
 
         /* Enable MPU */
         ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);