1 files changed, 36 insertions(+), 2 deletions(-)

M src/processor.rs

@@ 110,8 110,8 @@ impl <'a> Processor<'a> {
                         }
                     }
                     0x0003 => { //Division
-                        if self.reg[operands.2] == 0 && toggles.1 {self.flags[toggles.2 as usize] = true}
-                        else if self.reg[operands.2] != 0 {
+                        if self.reg[operands.1] == 0 && toggles.1 {self.flags[toggles.2 as usize] = true}
+                        else if self.reg[operands.1] != 0 {
                             if toggles.0 {
                                 self.reg[operands.2] = ((self.reg[operands.0] as i16)/(self.reg[operands.1] as i16)) as u16;
                             }


@@ 467,4 467,38 @@ mod tests {
         assert_eq!(processor.reg[2], u16::MAX - 1);
         assert_eq!(processor.reg[3], 5);
     }
+    #[test]
+    fn div () {
+        let memory: &mut [u16] = &mut [0x0600, 7, 0x0608, 3, 0x0103, 0x0044, 0, 0];
+        let disk: &mut [u16] = &mut [0];
+        let vram: &mut [u16] = &mut [0];
+        let mut processor = new(memory, disk, vram);
+        loop {
+            if processor.run() {break};
+        }
+        assert_eq!(processor.reg[2], 2);
+    }
+    #[test]
+    fn signed_div () { 
+        let memory: &mut [u16] = &mut [0x0600, 13, 0x0608, -4i16 as u16, 0x0183, 0x0044, 0, 0];
+        let disk: &mut [u16] = &mut [0];
+        let vram: &mut [u16] = &mut [0];
+        let mut processor = new(memory, disk, vram);
+        loop {
+            if processor.run() {break};
+        }
+        assert_eq!(processor.reg[2], -3i16 as u16);
+    }
+    #[test]
+    fn div_by_0 () {
+        let memory: &mut [u16] = &mut [0x0600, 5, 0x0143, 0x0044, 0xA618, 5, 0, 0];
+        let disk: &mut [u16] = &mut [0];
+        let vram: &mut [u16] = &mut [0];
+        let mut processor = new(memory, disk, vram);
+        loop {
+            if processor.run() {break};
+        }
+        assert_eq!(processor.reg[2], 0);
+        assert_eq!(processor.reg[3], 5);
+    }
 }