1 files changed, 35 insertions(+), 2 deletions(-)

M src/processor.rs

@@ 127,7 127,7 @@ impl <'a> Processor<'a> {
                 self.reg[31] += 2;
                 return false
             }
-            0x0200 => {
+            0x0200 => { //Logical
                 let toggles: (bool,bool,bool,bool) = ( //Z,F,R,I, see ISA for meanings
                     (instruction.0 & 0x0080) != 0,
                     (instruction.0 & 0x0040) != 0,


@@ 172,7 172,7 @@ impl <'a> Processor<'a> {
                 self.reg[31] += 2;
                 return false
             }
-            0x0300 => {
+            0x0300 => { //Condition check
                 let toggles: (bool, bool) = ( //Flag specifier, Invert
                     (instruction.0 & 0x0080) != 0,
                     (instruction.0 & 0x0040) != 0


@@ 557,4 557,37 @@ mod tests {
         assert_eq!(processor.reg[1], u16::MAX);
         assert_eq!(processor.reg[2], 5);
     }
+    #[test]
+    fn cond_eq() {
+        let mut memory = [0x0600, 3, 0x0608, 5, 0x0340, 0x0040, 0x0380, 0x0000, 0xF610, 5, 0, 0];
+        let mut disk = [0];
+        let mut vram = [0];
+        let mut processor = new(&mut memory, &mut disk, &mut vram);
+        loop {
+            if processor.run() {break};
+        }
+        assert_eq!(processor.reg[2], 5);
+    }
+    #[test]
+    fn cond_lt() {
+        let mut memory = [0x0600, 3, 0x0608, 5, 0x0310, 0x0040, 0xA610, 5, 0, 0];
+        let mut disk = [0];
+        let mut vram = [0];
+        let mut processor = new(&mut memory, &mut disk, &mut vram);
+        loop {
+            if processor.run() {break};
+        }
+        assert_eq!(processor.reg[2], 5);
+    }
+    #[test]
+    fn cond_lte() {
+        let mut memory = [0x0600, 3, 0x0608, 5, 0x0360, 0x0040, 0x03E0, 0x0000, 0xF610, 5, 0, 0];
+        let mut disk = [0];
+        let mut vram = [0];
+        let mut processor = new(&mut memory, &mut disk, &mut vram);
+        loop {
+            if processor.run() {break};
+        }
+        assert_eq!(processor.reg[2], 5);
+    }
 }