From 49699e0239f8d91e9179b13076ca577f165fe013 Mon Sep 17 00:00:00 2001
From: Madeline Cronin <maddie.henlo@gmail.com>
Date: Mon, 2 Sep 2024 22:24:44 +0100
Subject: [PATCH] Implement logical operations.

---
 src/processor.rs | 54 +++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 49 insertions(+), 5 deletions(-)

diff --git a/src/processor.rs b/src/processor.rs
index 70507bb..cb277ca 100644
--- a/src/processor.rs
+++ b/src/processor.rs
@@ -1,7 +1,7 @@
 pub struct Processor<'a> {
     reg: [u16;32],
-    flags: [bool;2], //flag A, then B
-    itr_toggle: bool,
+    flags: [bool;2], //Flag A, then B
+    itr_toggle: bool, //Interrupt toggle
     pub memory: &'a mut [u16], //Public since memory should be modifiable by the system.
     pub disk: &'a mut [u16], 
 }
@@ -51,7 +51,7 @@ impl <'a> Processor<'a> {
                 if operands.2 == 31 { //program counter is unwritable for non-control flow
                                       //instructions, but the overflow checks should still occur,
                                       //so hold onto the next value and replace it later.
-                    pc_overwrite = Some(self.reg[31] + 2);
+                    pc_overwrite = Some(self.reg[31]);
                 }
 
                 match instruction.0 & 0x000F {
@@ -65,7 +65,7 @@ impl <'a> Processor<'a> {
                                     (uncast_return as u16, flag)
                                 }
                                 else { //Otherwise just pass them straight to overflowing_add.
-                                    self.reg[operands.0].overflowing_add(self.reg[operands.1])
+                                   self.reg[operands.0].overflowing_add(self.reg[operands.1])
                                 }
                             };
                         }
@@ -103,7 +103,7 @@ impl <'a> Processor<'a> {
                             self.reg[operands.2] = self.reg[operands.0].wrapping_mul(self.reg[operands.1]);
                         }
                     }
-                    0x0003 => {
+                    0x0003 => { //Division
                         if self.reg[operands.2] == 0 && toggles.1 {self.flags[toggles.2 as usize] = true}
                         else if self.reg[operands.2] != 0 {
                             if toggles.0 {
@@ -118,6 +118,50 @@ impl <'a> Processor<'a> {
                 }
                 if toggles.3 {self.reg[operands.2] = !self.reg[operands.2]};
                 if let Some(addr) = pc_overwrite {self.reg[31] = addr};
+                self.reg[31] += 2;
+                return false
+            }
+            0x0200 => {
+                let toggles: (bool,bool,bool,bool) = ( //Z,F,R,I, see ISA for meanings
+                    (instruction.0 & 0x0080) != 0,
+                    (instruction.0 & 0x0040) != 0,
+                    (instruction.0 & 0x0020) != 0,
+                    (instruction.0 & 0x0010) != 0,
+                );
+                let operands: (usize, usize, usize) = (
+                    ((instruction.1 & 0xF800) >> 11) as usize,
+                    ((instruction.1 & 0x07C0) >> 6) as usize,
+                    ((instruction.1 & 0x004E) >> 1) as usize,
+                );
+                let mut pc_overwrite: Option<u16> = None;
+                if operands.2 == 31 { //program counter is unwritable for non-control flow
+                                      //instructions, but the non-zero checks should still occur,
+                                      //so hold onto the next value and replace it later.
+                    pc_overwrite = Some(self.reg[31]);
+                }
+
+                match instruction.0 & 0x000F {
+                    0x0000 => {
+                        self.reg[operands.2] = self.reg[operands.0] & self.reg[operands.1];
+                    }
+                    0x0001 => {
+                        self.reg[operands.2] = self.reg[operands.0] | self.reg[operands.1];
+                    }
+                    0x0002 => {
+                        self.reg[operands.2] = self.reg[operands.0] ^ self.reg[operands.1];
+                    }
+                    _ => return true
+                }
+                if toggles.3 {
+                    self.reg[operands.2] = !self.reg[operands.2];
+                };
+                if toggles.0 {
+                    self.flags[toggles.1 as usize] = (self.reg[operands.2] == 0) ^ toggles.2;
+                }
+                if let Some(addr) = pc_overwrite {
+                    self.reg[31] = addr;
+                }
+                self.reg[31] += 2;
                 return false
             }
             _ => return true,
-- 
2.43.4