From cb056663f4c780025f772277699f6c8aad5a05f5 Mon Sep 17 00:00:00 2001
From: Madeline Cronin <maddie.henlo@gmail.com>
Date: Mon, 2 Sep 2024 22:55:45 +0100
Subject: [PATCH] Implement condition check instructions.

---
 src/processor.rs | 30 ++++++++++++++++++++++++++++--
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/src/processor.rs b/src/processor.rs
index cb277ca..c0391eb 100644
--- a/src/processor.rs
+++ b/src/processor.rs
@@ -45,7 +45,7 @@ impl <'a> Processor<'a> {
                 let operands: (usize, usize, usize) = (
                     ((instruction.1 & 0xF800) >> 11) as usize,
                     ((instruction.1 & 0x07C0) >> 6) as usize,
-                    ((instruction.1 & 0x004E) >> 1) as usize,
+                    ((instruction.1 & 0x003E) >> 1) as usize,
                 );
                 let mut pc_overwrite: Option<u16> = None;
                 if operands.2 == 31 { //program counter is unwritable for non-control flow
@@ -131,7 +131,7 @@ impl <'a> Processor<'a> {
                 let operands: (usize, usize, usize) = (
                     ((instruction.1 & 0xF800) >> 11) as usize,
                     ((instruction.1 & 0x07C0) >> 6) as usize,
-                    ((instruction.1 & 0x004E) >> 1) as usize,
+                    ((instruction.1 & 0x003E) >> 1) as usize,
                 );
                 let mut pc_overwrite: Option<u16> = None;
                 if operands.2 == 31 { //program counter is unwritable for non-control flow
@@ -152,6 +152,7 @@ impl <'a> Processor<'a> {
                     }
                     _ => return true
                 }
+
                 if toggles.3 {
                     self.reg[operands.2] = !self.reg[operands.2];
                 };
@@ -161,6 +162,31 @@ impl <'a> Processor<'a> {
                 if let Some(addr) = pc_overwrite {
                     self.reg[31] = addr;
                 }
+
+                self.reg[31] += 2;
+                return false
+            }
+            0x0300 => {
+                let toggles: (bool, bool) = ( //Flag specifier, Invert
+                    (instruction.0 & 0x0080) != 0,
+                    (instruction.0 & 0x0040) != 0
+                );
+                let operands: (usize, usize) = (
+                    ((instruction.1 & 0xF800) >> 11) as usize,
+                    ((instruction.1 & 0x07C0) >> 6) as usize,
+                );
+                match instruction.0 & 0x0030 {
+                    0x0000 => {
+                        self.flags[toggles.0 as usize] = (self.reg[operands.0] == self.reg[operands.1]) ^ toggles.1;
+                    }
+                    0x0010 => {
+                        self.flags[toggles.0 as usize] = (self.reg[operands.0] < self.reg[operands.1]) ^ toggles.1;
+                    }
+                    0x0020 => {
+                        self.flags[toggles.0 as usize] = (self.reg[operands.0] > self.reg[operands.1]) ^ toggles.1;
+                    }
+                    _ => return true
+                }
                 self.reg[31] += 2;
                 return false
             }
-- 
2.43.4