From 45e266958cc47af7a590d63a383c14aad28c33f2 Mon Sep 17 00:00:00 2001 From: Madeline Cronin Date: Sat, 24 Aug 2024 23:32:30 +0100 Subject: [PATCH] Second pass for overview and instruction categories. Made the overview easier to read by grouping details more sensibly, and made the descriptions in the instruction categories more consistent. --- mta_v1.0.txt | 141 +++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 119 insertions(+), 22 deletions(-) diff --git a/mta_v1.0.txt b/mta_v1.0.txt index 1255e9b..155d44c 100644 --- a/mta_v1.0.txt +++ b/mta_v1.0.txt @@ -3,31 +3,128 @@ Maddie's test ISA Version 1.0 Table of contents: 1 - Overview -2 - Instruction composition +2 - Instruction conditions 3 - Instruction categories 4 - Instruction descriptions +- Overview: +The numbers: 16 bit words, 2-word fixed instruction length, 32 16-bit registers, +65535 main memory and VRAM addresses each, 2^32 max disc addresses. -Overview: -- TODO: clean up for readability -This is a simplistic 16 bit RISC ISA, which describes a largely stateless CPU, the only -statefulness that is described is the ability to toggle interrupts. -There are no described SIMD or floating point capabilities, this will likely change -in future versions of this ISA. -The versioning is delineated such that minor versions are backwards compatible, while major versions are not. -The serial port is primarily designed for interfacing with STDIN/STDOUT in simulated versions, -although it may be useful in hardware also. -Interrupts can either be triggered by software, for the purposes of providing a standard location in memory, -or triggered by hardware, for now this is just for keyboard interrupts. -One major feature is that all instructions have the option to have a condition attached, located in the first -four bits of each instruction, functioning as two toggles and two requirements, in order to facilitate -negative conditons. -This ISA describes a CPU with variable length instructions, a combined program and general purpose RAM, -and a 16 bit word length, with registers to match. -Memory is word addressable, and up to 65535 main memory addresses are available, with up to 2^32 words of -disk space accessible through use of the disk index register. -There are 32 registers, the first of which is reserved for interrupts, software or otherwise. -Upon boot, the first 512 words of disk are copied to main memory. - -Instruction categories: +Features: All instructions can have conditional execution attached. +Hardware and software interrupts are toggleable. Serial port I/O intended for +interfacing with STDIN/STDOUT on simulated versions. +Registers: 32 registers, with registers #28-31 (zero indexed) reserved for the +following special purposes, in order: disk index, stack pointer, program +counter, and interrupt register. The program counter is freely readable, but +only modifiable through instructions in the control flow category. There is +also a 2 bit flags register for storing the condition flags. + +Behaviours: Upon power up, the first 512 words of disk are copied to main +memory. The only statefulness not directly controlled by programs is the +interrupt toggle. + +Versioning: The versioning of this ISA is such that minor versions are +backwards compatible, while major versions have one or more breaking changes +that may mean old code no longer works. + +Notes for reading: In the description of a bit or collection of bits for an +instruction, anything following a tag such as (A=1) means that any behaviours +described between that tag and the next tag, or end of line, are only followed +when the condition in the tag is met. If no conditions are met, no additional +behaviour is to occur. + + +- Instruction Conditions: +ABab----|--------|--------|-------- +AB = Activation Flags +ab = Condition Flags +There is a 2 bit register in the CPU which stores the state of A and B, and is +updated by certain instructions. +When an activation flag is set, the corresponding condition bit must match its +condition flag in order for the instruction to be executed. + +- Instruction Categories: +----XXXX|--------|--------|--------- +XXXX= +0000: Halt +0001: Arithmetic +0010: Logical +0011: Condition Check +0100: Control Flow +0101: Memory Access +0110: Immediate Value +1111: No-op + +Halt: +----0000|--------|--------|--------- +Halts the processor. + +Arithmetic: +----0001|SCFIXXXX|--------|--------- +S: Input is (S=0) unsigned, (S=1) signed using 2's complement +C: (C=1) Update the specified condition flag upon overflow +F: Specifies (F=0) flag A or (F=1) flag B +I: (I=1) Invert the result + +XXXX= +0000: Addition +0001: Subtraction +0010: Multiplication +0011: Integer Division + +Logical: +----0010|ZFRIXXXX|--------|-------- +Z: (Z=1) Update the specified condition flag if the result is zero +F: Specifies (F=0) flag A or (F=1) flag B +R: (I=1) Invert the flag write +I: (I=1) Invert the result, acts before the zero check + +XXXX= +0000: AND +0001: OR +0010: XOR + +Condition check: +----0011|FIXX----|--------|-------- +F: (I=1) Invert the flag write +I: (I=0) Normal write, (I=1) inverted write + +XX= +00: Equal +01: Less than +10: Greater than + +Control flow: +----0100|JSPITT--|--------|-------- +J: (J=0) Jump to the described address, (J=1) Add the described value to the +program counter +S: (S=1) Push the current address to the stack +P: (P=1) Pop from the stack and use the stack value instead of a register +value +I: (I=1) If interrupts are enabled, jump to 0. This overrides J and P, +preventing the pop from occuring. Note that if interrupts are disabled then J +and P will work normally. + +TT= +0x: No additional effect +10: Toggle interrupts off +11: Toggle interrupts on, both of these operations act before the condition +check for I=1 + +Memory access: +----0101|AXXX----|--------|-------- +A: (A=0) Read/pop, (A=1) Write/push + +XXX= +000: Pop/push to stack +001: Read/write RAM +010: R/W disk +011: R/W VRAM +100: R/W to serial port + +Immediate value: +----0110|RRRRR---|xxxxxxxx|xxxxxxxx +Writes the value denoted by x's to the register of index RRRRR -- 2.43.4