From 6036dd922cc4ce59908747d0dbc0b65ec9879c10 Mon Sep 17 00:00:00 2001 From: Madeline Cronin Date: Tue, 13 Aug 2024 22:28:05 +0100 Subject: [PATCH] Initial Commit Add first and second draft of spec and unfinished first version --- .gitignore | 2 + mta_v1.0.txt | 33 ++++++++++++ processor_spec_first_draft.txt | 93 +++++++++++++++++++++++++++++++++ processor_spec_second_draft.txt | 75 ++++++++++++++++++++++++++ 4 files changed, 203 insertions(+) create mode 100644 .gitignore create mode 100644 mta_v1.0.txt create mode 100644 processor_spec_first_draft.txt create mode 100644 processor_spec_second_draft.txt diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b72f9be --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +*~ +*.swp diff --git a/mta_v1.0.txt b/mta_v1.0.txt new file mode 100644 index 0000000..1255e9b --- /dev/null +++ b/mta_v1.0.txt @@ -0,0 +1,33 @@ +Maddie's test ISA Version 1.0 + + +Table of contents: +1 - Overview +2 - Instruction composition +3 - Instruction categories +4 - Instruction descriptions + + + +Overview: -- TODO: clean up for readability +This is a simplistic 16 bit RISC ISA, which describes a largely stateless CPU, the only +statefulness that is described is the ability to toggle interrupts. +There are no described SIMD or floating point capabilities, this will likely change +in future versions of this ISA. +The versioning is delineated such that minor versions are backwards compatible, while major versions are not. +The serial port is primarily designed for interfacing with STDIN/STDOUT in simulated versions, +although it may be useful in hardware also. +Interrupts can either be triggered by software, for the purposes of providing a standard location in memory, +or triggered by hardware, for now this is just for keyboard interrupts. +One major feature is that all instructions have the option to have a condition attached, located in the first +four bits of each instruction, functioning as two toggles and two requirements, in order to facilitate +negative conditons. +This ISA describes a CPU with variable length instructions, a combined program and general purpose RAM, +and a 16 bit word length, with registers to match. +Memory is word addressable, and up to 65535 main memory addresses are available, with up to 2^32 words of +disk space accessible through use of the disk index register. +There are 32 registers, the first of which is reserved for interrupts, software or otherwise. +Upon boot, the first 512 words of disk are copied to main memory. + +Instruction categories: + diff --git a/processor_spec_first_draft.txt b/processor_spec_first_draft.txt new file mode 100644 index 0000000..2d8dac4 --- /dev/null +++ b/processor_spec_first_draft.txt @@ -0,0 +1,93 @@ +conditional exec on all +14 registers(ID 0-13) + stack pointer(ID 14) + program counter(ID 15) --- NO ELEGANT WAY TO ACCESS DISK, MORE SPECIALISED REGISTERS WOULD BE HELPFUL, THOUGH SIMD IS NOT A GOAL IN THIS PROJECT +8 bit instructions, 16 bit values --- TOO CRAMPED, VARIATION BETWEEN INSTUCTION AND DATA WIDTH IS IFFY +4 byte constant instruction width --- UNSURE WHETHER THE PACKING BONUS OF VARIABLE LENGTH IS WORTH THE COMPLEXITY FOR NOW +16 bit address space -> 64Kib memory, disk is 256 blocks of 64Kib for 16Mib --- 16BIT IS GOOD FOR A SIMPLE PROJECT BUT PROBABLY TOO CRAMPED FOR LARGER TASKS, KEEP AS IS +black and white display, 64x64 pixel display, last 4Kib of memory is mapped to display --- CANABBALISING RAM IS IFFY, DEDICATED INSTRUCTIONS FEEL IFFY AS WELL BUT WITH LARGER INSTRUCTION SPACE WOULD BE PREFERABLE + + + +bits 1-2 determine the conditions upon which the command is executed --- NO GOOD WAY TO DO UNCONDITIONAL EXECUTION AND NEGATIVE CHECKS SIMULTANEOUSLY, EXTRA FLAG BIT WOULD BE IDEAL +00 = false boolean check +11 = true boolean check or equal equivalence check +10 = greater than equivalence check +01 = less than equivalence check + +bits 3-5 determine category of instructions --- DECIDE INSTRUCTION GROUPS FIRST, AND GROUP UP IN SENSIBLE WAYS, RATHER THAN FIRST COME FIRST SERVE +000 = immediate value --- INSTRUCTION PARAMATER IMMEDIACY CAN BE USEFUL, BUT A DEDICATED IMMEDIATE INSTRUCTION CAN BE MORE EFFICIENT THAN A NO-OP SUCH AS OR WITH 0 ON IMMEDIATES, MAYBE USE BOTH +001 = arithmetic +010 = logical +011 = condition check +100 = memory access +101 = control flow +111 = halt + +--- SOME KIND OF PRIVELEDGES SYSTEM WOULD BE USEFUL BUT LIKELY OUT OF SCOPE FOR WHAT AMOUNTS TO A TEST PROJECT, SIMILARLY FOR MANAGED MEMORY BLOCKS + +bits 6-8 determine specific instructions + +immediate: +not used + +arithmetic: +x00 = addition +x01 = subtraction +x10 = multiplication +x11 = negative --- WHAT DID THEY MEAN BY THIS +1xx = invert output + +logical: +x00 = or +x01 = and +x10 = xor +1xx = invert output + +condition check: +x00 = compare +x01 = add with overflow check +x10 = subtract with underflow check +x11 = multiply with overflow check --- PROBABLY BEST GROUPED INTO ARITHMETIC AS A FLAG THERE +1xx = invert flags + +memory access: --- BETTER SYSTEM FOR ADDRESSING MEMORY WOULD BE USEFUL, PROBABLY IN THE FORM OF A DEDICATED, WRITE LOCKED REGISTER ALTERED THROUGH MEMORY ACCESS COMMANDS +000 = push +001 = pop +010 = store +011 = load +100 = store to disk +101 = load from disk +110 = output to serial port +111 = input from serial port + +control flow: --- INTERRUPTS AS PART OF CONTROL FLOW WOULD BE USEFUL BUT ONLY REALLY IMPACTFUL AS PART OF THE PRIVELEDGE SYSTEM, OTHERWISE THEY AREN'T MEANINGFULLY DIFFERENT FROM A STATIC JUMP +000 = static jump +001 = additive jump +010 = push pc and static jump +011 = push pc and additive jump +100 = enable interrupts +101 = disable interrupts + + + + +bytes 2 and 3 (usually) determine inputs --- INCREASE TO 16 BITS TO MATCH INSTRUCTION LENGTH INCREASE + +immediate: bytes 2 and 3 are combined into a 16 bit value --- THIS SUCKS + +arithmetic, logical, and condition check: bytes 2 and 3 are register indices, wrapping mod 16 --- PROBABLY GOING TO BE MOD 32 DUE TO REGISTER COUNT INCREASE + +memory access: bytes 2 and 3 get merged into one 16 bit load/store address, discarded on push/pop --- THIS ALSO SUCKS + +control flow: discarded --- WHAT DO YOU MEAN DISCARDED YOU FUC- + + + +byte 4 is (usually) the output, and always refers to a register + +immediate: index of register to store immediate value in, wrapping mod 16 + +arithmetic and logical: index of register to store result in, wrapping mod 16 --- REGISTER COUNT INCREASE APPLIES HERE AS WELL + +condition check: index of register to store result of checked arithmetic operations in, wrapping mod 16 + +memory access: index of register to interact with, wrapping mod 16 --- THIS WOULD BE BETTER OMITTED BY VARIABLE LENGTH INSTRUCTIONS \ No newline at end of file diff --git a/processor_spec_second_draft.txt b/processor_spec_second_draft.txt new file mode 100644 index 0000000..b8b40cd --- /dev/null +++ b/processor_spec_second_draft.txt @@ -0,0 +1,75 @@ +16 bit instructions, variable length +each additional 16 bit value represents either a register or immediate value, any register indices are wrapped mod 32 +32 total registers, incl. program counter, stack pointer, and disk index +index 0 is reserved for passing data in interrupts, pc, sp, and disk index are index 31, 30, and 29 respectively +16 bit address space for ram, dedicated vram accessed by separate instructions, also 64Kib, for a 256x256 B/W display +32 bit address space for disk, split into 64Kib blocks indexed by register - 4GB is definitely too much for a test project, but the capability can exist for the sake of it. + +bits 1-4 determine the conditions upon which the command is executed +0xxx = flag 1 unchecked +x0xx = flag 2 unchecked +1x0x = flag 1 is 0 +1x1x = flag 1 is 1 +x1x0 = flag 2 is 0 +x1x1 = flag 2 is 1 +first 2 bits are activations, second 2 bits are conditions + + +bits 5-8 determine the instruction category +0000 = halt +0001 = arithmetic +0010 = logical +0011 = condition check +0100 = control flow +0101 = memory access + + +bits 9-14 determine the specific instruction + +arithmetic: - 2 REG IN, 1 REG OUT on all +xx00 = addition +xx01 = subtraction +xx10 = multiplication +xx11 = division +x1xx = set flag 1 on overflow +1xxx = invert output + +logical: - 2 REG IN, 1 REG OUT on all +xx00 = and +xx01 = or +xx10 = xor +x1xx = invert output +1xxx = set flag 2 if nonzero result + +condition check: - 2 REG IN on all +0xxx = write to flag 1 +1xxx = write to flag 2 +x0xx = normal write +x1xx = inverted write +xx00 = equal +xx01 = greater than +xx10 = less than + +control flow: - 1 REG IN +00x0 = static jump +00x1 = relative jump +0x1x = push pc before jump +01x0 = pop to pc - NO ADDITIONAL INPUTS +01x1 = interrupt (jump to 0) - NO ADDITIONAL INPUTS +1000 = enable interrupts - NO ADDITIONAL INPUTS +1001 = disable interrupts (default) - NO ADDITIONAL INPUTS + +memory access: - 2 REG IN, TARGET REG, THEN ADDRESS REG +0000 = push - 1 REG IN +0001 = pop - 1 REG IN, NO IMMEDIATE +xx10 = store +xx11 = load - NO IMMEDIATE ON TARGET REG +001x = access RAM +011x = access DISK +101x = access VRAM +111x = serial port I/O + + +bits 15-16 determine input immediacy: +1x = 1st input (if used) is an immediate value +x1 = 2nd input (if used) is an immediate value -- 2.43.4