D board/linux/macros.h => board/linux/macros.h +0 -74
@@ 1,74 0,0 @@
-/*
- * @file macros.h
- * @author Mateusz Piesta (mateusz.piesta@mudita.com)
- * @date 31 lip 2018
- * @brief Handy macros
- * @copyright Copyright (C) 2018 mudita.com
- * @details
- */
-
-#ifndef MACROS_H_
-#define MACROS_H_
-
-#include <stdbool.h>
-#include <assert.h>
-#include <stdint.h>
-
-#define _STRINGIFY(s) #s
-#define STRINGIFY(s) _STRINGIFY(s)
-
-#define UNUSED(x) ((void)(x))
-
-#define ALIGN_(n) __attribute__((aligned(n)))
-
-#define CACHEABLE_SECTION_SDRAM(var) var
-
-#define CACHEABLE_SECTION_SDRAM_ALIGN(var, alignbytes) var
-
-#define NONCACHEABLE_SECTION_SDRAM(var) var
-
-#define NONCACHEABLE_SECTION_SDRAM_ALIGN(var, alignbytes) var
-
-#define NONCACHEABLE_SECTION_INIT(var) var
-
-#define NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
-
-#define NONCACHEABLE_SECTION(var) var
-
-#define NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
-
-static inline uint32_t IS_MEM_ADDR_CACHED(void *addr)
-{
- extern uint32_t __sdram_non_cached_start[];
- extern uint32_t __sdram_non_cached_end[];
- extern uint32_t __ocram_cached_start[];
- extern uint32_t __ocram_cached_end[];
- extern uint32_t __dtcm_ram_start[];
- extern uint32_t __dtcm_ram_end[];
- extern uint32_t __sdram_cached_start[];
- extern uint32_t __sdram_cached_end[];
-
- if (((uint32_t *)addr >= (uint32_t *)__sdram_non_cached_start) &&
- ((uint32_t *)addr < (uint32_t *)__sdram_non_cached_end)) {
- return 0;
- }
- if (((uint32_t *)addr >= (uint32_t *)__ocram_cached_start) && ((uint32_t *)addr < (uint32_t *)__ocram_cached_end)) {
- return 1;
- }
- if (((uint32_t *)addr >= (uint32_t *)__dtcm_ram_start) && ((uint32_t *)addr < (uint32_t *)__dtcm_ram_end)) {
- return 0;
- }
- if (((uint32_t *)addr >= (uint32_t *)__sdram_cached_start) && ((uint32_t *)addr < (uint32_t *)__sdram_cached_end)) {
- return 1;
- }
-
- assert(0);
-}
-
-//! Test if in interrupt mode
-static inline bool isIRQ()
-{
- return false;
-}
-
-#endif /* MACROS_H_ */
M board/rt1051/CMakeLists.txt => board/rt1051/CMakeLists.txt +1 -1
@@ 1,3 1,4 @@
+add_subdirectory(cmsis)
add_subdirectory(${BOARD})
if (${MEMORY_LINKER_FILE_PATH} STREQUAL "")
@@ 8,7 9,6 @@ set (CMAKE_EXE_LINKER_FLAGS "-nostdlib -Xlinker --gc-sections -Xlinker --sort-se
target_sources(board
PRIVATE
- _exit.c
crashdump/consoledump.cpp
crashdump/crashcatcher_impl.cpp
crashdump/crashdumpwriter_vfs.cpp
A board/rt1051/cmsis/CMakeLists.txt => board/rt1051/cmsis/CMakeLists.txt +30 -0
@@ 0,0 1,30 @@
+add_library(cmsis INTERFACE)
+
+target_include_directories(cmsis
+ INTERFACE
+ $<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}>
+)
+
+target_sources(cmsis
+ INTERFACE
+ arm_common_tables.h
+ arm_const_structs.h
+ arm_math.h
+ CMakeLists.txt
+ cmsis_armcc.h
+ cmsis_armclang.h
+ cmsis_compiler.h
+ cmsis_gcc.h
+ cmsis_iccarm.h
+ cmsis_version.h
+ core_armv8mbl.h
+ core_armv8mml.h
+ core_cm7.h
+ MIMXRT1051_features.h
+ MIMXRT1051.h
+ MIMXRT1052_features.h
+ MIMXRT1052.h
+ mpu_armv7.h
+ mpu_armv8.h
+ system_MIMXRT1051.h
+)
R module-bsp/board/rt1051/common/cmsis/MIMXRT1051.h => board/rt1051/cmsis/MIMXRT1051.h +27 -19
@@ 27654,14 27654,14 @@ typedef struct
uint8_t RESERVED_0[12];
__I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */
uint8_t RESERVED_1[12];
- __IO uint32_t LOOPBACK; /**< USB Loopback Test Register, array offset: 0x1E0, array step: 0x60 */
- __IO uint32_t LOOPBACK_SET; /**< USB Loopback Test Register, array offset: 0x1E4, array step: 0x60 */
- __IO uint32_t LOOPBACK_CLR; /**< USB Loopback Test Register, array offset: 0x1E8, array step: 0x60 */
- __IO uint32_t LOOPBACK_TOG; /**< USB Loopback Test Register, array offset: 0x1EC, array step: 0x60 */
- __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */
- __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */
- __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */
- __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */
+ __IO uint32_t LOOPBACK; /**< USB Loopback Test Register, array offset: 0x1E0, array step: 0x60 */
+ __IO uint32_t LOOPBACK_SET; /**< USB Loopback Test Register, array offset: 0x1E4, array step: 0x60 */
+ __IO uint32_t LOOPBACK_CLR; /**< USB Loopback Test Register, array offset: 0x1E8, array step: 0x60 */
+ __IO uint32_t LOOPBACK_TOG; /**< USB Loopback Test Register, array offset: 0x1EC, array step: 0x60 */
+ __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */
+ __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */
+ __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */
+ __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */
} INSTANCE[2];
__I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */
} USB_ANALOG_Type;
@@ 27924,41 27924,49 @@ typedef struct
/*! @{ */
#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
-#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
+#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) \
+ (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & \
+ USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
/*! @} */
/* The count of USB_ANALOG_LOOPBACK */
-#define USB_ANALOG_LOOPBACK_COUNT (2U)
+#define USB_ANALOG_LOOPBACK_COUNT (2U)
/*! @name LOOPBACK_SET - USB Loopback Test Register */
/*! @{ */
-#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
+#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
-#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
+#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) \
+ (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & \
+ USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
/*! @} */
/* The count of USB_ANALOG_LOOPBACK_SET */
-#define USB_ANALOG_LOOPBACK_SET_COUNT (2U)
+#define USB_ANALOG_LOOPBACK_SET_COUNT (2U)
/*! @name LOOPBACK_CLR - USB Loopback Test Register */
/*! @{ */
-#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
+#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
-#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
+#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) \
+ (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & \
+ USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
/*! @} */
/* The count of USB_ANALOG_LOOPBACK_CLR */
-#define USB_ANALOG_LOOPBACK_CLR_COUNT (2U)
+#define USB_ANALOG_LOOPBACK_CLR_COUNT (2U)
/*! @name LOOPBACK_TOG - USB Loopback Test Register */
/*! @{ */
-#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
+#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
-#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
+#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) \
+ (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & \
+ USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
/*! @} */
/* The count of USB_ANALOG_LOOPBACK_TOG */
-#define USB_ANALOG_LOOPBACK_TOG_COUNT (2U)
+#define USB_ANALOG_LOOPBACK_TOG_COUNT (2U)
/*! @name MISC - USB Misc Register */
/*! @{ */
R module-bsp/board/rt1051/common/cmsis/MIMXRT1051_features.h => board/rt1051/cmsis/MIMXRT1051_features.h +0 -0
R module-bsp/board/rt1051/common/cmsis/MIMXRT1052.h => board/rt1051/cmsis/MIMXRT1052.h +27 -19
@@ 27654,14 27654,14 @@ typedef struct
uint8_t RESERVED_0[12];
__I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */
uint8_t RESERVED_1[12];
- __IO uint32_t LOOPBACK; /**< USB Loopback Test Register, array offset: 0x1E0, array step: 0x60 */
- __IO uint32_t LOOPBACK_SET; /**< USB Loopback Test Register, array offset: 0x1E4, array step: 0x60 */
- __IO uint32_t LOOPBACK_CLR; /**< USB Loopback Test Register, array offset: 0x1E8, array step: 0x60 */
- __IO uint32_t LOOPBACK_TOG; /**< USB Loopback Test Register, array offset: 0x1EC, array step: 0x60 */
- __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */
- __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */
- __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */
- __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */
+ __IO uint32_t LOOPBACK; /**< USB Loopback Test Register, array offset: 0x1E0, array step: 0x60 */
+ __IO uint32_t LOOPBACK_SET; /**< USB Loopback Test Register, array offset: 0x1E4, array step: 0x60 */
+ __IO uint32_t LOOPBACK_CLR; /**< USB Loopback Test Register, array offset: 0x1E8, array step: 0x60 */
+ __IO uint32_t LOOPBACK_TOG; /**< USB Loopback Test Register, array offset: 0x1EC, array step: 0x60 */
+ __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */
+ __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */
+ __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */
+ __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */
} INSTANCE[2];
__I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */
} USB_ANALOG_Type;
@@ 27924,41 27924,49 @@ typedef struct
/*! @{ */
#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
-#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
+#define USB_ANALOG_LOOPBACK_UTMI_TESTSTART(x) \
+ (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_UTMI_TESTSTART_SHIFT)) & \
+ USB_ANALOG_LOOPBACK_UTMI_TESTSTART_MASK)
/*! @} */
/* The count of USB_ANALOG_LOOPBACK */
-#define USB_ANALOG_LOOPBACK_COUNT (2U)
+#define USB_ANALOG_LOOPBACK_COUNT (2U)
/*! @name LOOPBACK_SET - USB Loopback Test Register */
/*! @{ */
-#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
+#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
-#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
+#define USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART(x) \
+ (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & \
+ USB_ANALOG_LOOPBACK_SET_UTMI_TESTSTART_MASK)
/*! @} */
/* The count of USB_ANALOG_LOOPBACK_SET */
-#define USB_ANALOG_LOOPBACK_SET_COUNT (2U)
+#define USB_ANALOG_LOOPBACK_SET_COUNT (2U)
/*! @name LOOPBACK_CLR - USB Loopback Test Register */
/*! @{ */
-#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
+#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
-#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
+#define USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART(x) \
+ (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & \
+ USB_ANALOG_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
/*! @} */
/* The count of USB_ANALOG_LOOPBACK_CLR */
-#define USB_ANALOG_LOOPBACK_CLR_COUNT (2U)
+#define USB_ANALOG_LOOPBACK_CLR_COUNT (2U)
/*! @name LOOPBACK_TOG - USB Loopback Test Register */
/*! @{ */
-#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
+#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
-#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
+#define USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART(x) \
+ (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & \
+ USB_ANALOG_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
/*! @} */
/* The count of USB_ANALOG_LOOPBACK_TOG */
-#define USB_ANALOG_LOOPBACK_TOG_COUNT (2U)
+#define USB_ANALOG_LOOPBACK_TOG_COUNT (2U)
/*! @name MISC - USB Misc Register */
/*! @{ */
R module-bsp/board/rt1051/common/cmsis/MIMXRT1052_features.h => board/rt1051/cmsis/MIMXRT1052_features.h +0 -0
R module-bsp/board/rt1051/common/cmsis/arm_common_tables.h => board/rt1051/cmsis/arm_common_tables.h +0 -0
R module-bsp/board/rt1051/common/cmsis/arm_const_structs.h => board/rt1051/cmsis/arm_const_structs.h +1 -1
@@ 31,7 31,7 @@
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
-#include "cmsis/arm_common_tables.h"
+#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
R module-bsp/board/rt1051/common/cmsis/arm_math.h => board/rt1051/cmsis/arm_math.h +0 -0
R module-bsp/board/rt1051/common/cmsis/cmsis_armcc.h => board/rt1051/cmsis/cmsis_armcc.h +0 -0
R module-bsp/board/rt1051/common/cmsis/cmsis_armclang.h => board/rt1051/cmsis/cmsis_armclang.h +0 -0
R module-bsp/board/rt1051/common/cmsis/cmsis_compiler.h => board/rt1051/cmsis/cmsis_compiler.h +0 -0
R module-bsp/board/rt1051/common/cmsis/cmsis_gcc.h => board/rt1051/cmsis/cmsis_gcc.h +0 -0
R module-bsp/board/rt1051/common/cmsis/cmsis_iccarm.h => board/rt1051/cmsis/cmsis_iccarm.h +0 -0
R module-bsp/board/rt1051/common/cmsis/cmsis_version.h => board/rt1051/cmsis/cmsis_version.h +0 -0
R module-bsp/board/rt1051/common/cmsis/core_armv8mbl.h => board/rt1051/cmsis/core_armv8mbl.h +42 -29
@@ 1050,8 1050,9 @@ extern "C"
(1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask \
- */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk \
+ (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask \
+ */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk \
@@ 1070,8 1071,9 @@ extern "C"
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask \
- */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk \
+ (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask \
+ */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
@@ 1080,8 1082,9 @@ extern "C"
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask \
- */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk \
+ (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask \
+ */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
@@ 1095,8 1098,9 @@ extern "C"
#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask \
- */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk \
+ (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask \
+ */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk \
@@ 1292,8 1296,9 @@ extern "C"
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1326,8 1331,9 @@ extern "C"
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1371,8 1377,9 @@ extern "C"
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1390,8 1397,9 @@ extern "C"
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1408,8 1416,9 @@ extern "C"
{
if ((int32_t)(IRQn) >= 0) {
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return ((uint32_t)(
- ((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1426,8 1435,9 @@ extern "C"
{
if ((int32_t)(IRQn) >= 0) {
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return ((uint32_t)(
- ((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1558,9 1568,10 @@ extern "C"
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL
- : 0UL));
+ return (
+ (uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1590,9 1601,10 @@ extern "C"
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL
- : 0UL));
+ return (
+ (uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1633,9 1645,10 @@ extern "C"
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL
- : 0UL));
+ return (
+ (uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
R module-bsp/board/rt1051/common/cmsis/core_armv8mml.h => board/rt1051/cmsis/core_armv8mml.h +57 -41
@@ 730,8 730,9 @@ extern "C"
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask \
- */
+#define SCB_CFSR_USGFAULTSR_Msk \
+ (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask \
+ */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
@@ 1882,8 1883,9 @@ extern "C"
(1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask \
- */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk \
+ (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask \
+ */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk \
@@ 1906,8 1908,9 @@ extern "C"
(1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask \
- */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk \
+ (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask \
+ */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
@@ 1916,8 1919,9 @@ extern "C"
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask \
- */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk \
+ (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask \
+ */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
@@ 1943,8 1947,9 @@ extern "C"
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask \
- */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk \
+ (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask \
+ */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
@@ 1953,15 1958,17 @@ extern "C"
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask \
- */
+#define CoreDebug_DEMCR_VC_STATERR_Msk \
+ (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask \
+ */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask \
- */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk \
+ (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask \
+ */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
@@ 2196,8 2203,9 @@ extern "C"
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 2230,8 2238,9 @@ extern "C"
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 2275,8 2284,9 @@ extern "C"
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 2294,8 2304,9 @@ extern "C"
__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 2312,8 2323,9 @@ extern "C"
{
if ((int32_t)(IRQn) >= 0) {
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return ((uint32_t)(
- ((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 2330,8 2342,9 @@ extern "C"
{
if ((int32_t)(IRQn) >= 0) {
NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return ((uint32_t)(
- ((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 2399,9 2412,9 @@ extern "C"
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS))
? (uint32_t)(__NVIC_PRIO_BITS)
: (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL)
- ? (uint32_t)0UL
- : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL)
+ ? (uint32_t)0UL
+ : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
@@ 2430,9 2443,9 @@ extern "C"
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS))
? (uint32_t)(__NVIC_PRIO_BITS)
: (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL)
- ? (uint32_t)0UL
- : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL)
+ ? (uint32_t)0UL
+ : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
@@ 2539,9 2552,10 @@ extern "C"
__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL
- : 0UL));
+ return (
+ (uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 2571,9 2585,10 @@ extern "C"
__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL
- : 0UL));
+ return (
+ (uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 2614,9 2629,10 @@ extern "C"
__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL
- : 0UL));
+ return (
+ (uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
R module-bsp/board/rt1051/common/cmsis/core_cm7.h => board/rt1051/cmsis/core_cm7.h +36 -26
@@ 657,8 657,9 @@ extern "C"
/* SCB Configurable Fault Status Register Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask \
- */
+#define SCB_CFSR_USGFAULTSR_Msk \
+ (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask \
+ */
#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
@@ 1634,8 1635,9 @@ extern "C"
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask \
- */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk \
+ (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask \
+ */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk \
@@ 1658,8 1660,9 @@ extern "C"
(1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask \
- */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk \
+ (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask \
+ */
#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
@@ 1668,8 1671,9 @@ extern "C"
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask \
- */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk \
+ (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask \
+ */
/* Debug Core Register Selector Register Definitions */
#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
@@ 1695,8 1699,9 @@ extern "C"
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask \
- */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk \
+ (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask \
+ */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
@@ 1705,15 1710,17 @@ extern "C"
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask \
- */
+#define CoreDebug_DEMCR_VC_STATERR_Msk \
+ (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask \
+ */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask \
- */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk \
+ (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask \
+ */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
@@ 1892,8 1899,9 @@ extern "C"
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1926,8 1934,9 @@ extern "C"
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 1971,8 1980,9 @@ extern "C"
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0) {
- return ((uint32_t)(
- ((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL)
+ ? 1UL
+ : 0UL));
}
else {
return (0U);
@@ 2039,9 2049,9 @@ extern "C"
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS))
? (uint32_t)(__NVIC_PRIO_BITS)
: (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL)
- ? (uint32_t)0UL
- : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL)
+ ? (uint32_t)0UL
+ : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))));
@@ 2070,9 2080,9 @@ extern "C"
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS))
? (uint32_t)(__NVIC_PRIO_BITS)
: (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL)
- ? (uint32_t)0UL
- : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL)
+ ? (uint32_t)0UL
+ : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL);
R module-bsp/board/rt1051/common/cmsis/mpu_armv7.h => board/rt1051/cmsis/mpu_armv7.h +0 -0
R module-bsp/board/rt1051/common/cmsis/mpu_armv8.h => board/rt1051/cmsis/mpu_armv8.h +0 -0
R module-bsp/board/rt1051/common/system_MIMXRT1051.h => board/rt1051/cmsis/system_MIMXRT1051.h +0 -0
M module-bsp/board/rt1051/CMakeLists.txt => module-bsp/board/rt1051/CMakeLists.txt +3 -32
@@ 34,36 34,6 @@ target_sources(module-bsp
common/audio.cpp
common/board.cpp
common/chip.cpp
- common/fsl_drivers/fsl_adc.c
- common/fsl_drivers/fsl_cache.c
- common/fsl_drivers/fsl_clock.c
- common/fsl_drivers/fsl_clock.c
- common/fsl_drivers/fsl_common.c
- common/fsl_drivers/fsl_dcdc.c
- common/fsl_drivers/fsl_dmamux.c
- common/fsl_drivers/fsl_edma.c
- common/fsl_drivers/fsl_flexram.c
- common/fsl_drivers/fsl_gpc.c
- common/fsl_drivers/fsl_gpio.c
- common/fsl_drivers/fsl_gpt.c
- common/fsl_drivers/fsl_lpi2c.c
- common/fsl_drivers/fsl_lpspi_edma.c
- common/fsl_drivers/fsl_lpspi.c
- common/fsl_drivers/fsl_lpuart_edma.c
- common/fsl_drivers/fsl_lpuart.c
- common/fsl_drivers/fsl_pit.c
- common/fsl_drivers/fsl_pmu.c
- common/fsl_drivers/fsl_pwm.c
- common/fsl_drivers/fsl_rtwdog.c
- common/fsl_drivers/fsl_sai_edma.c
- common/fsl_drivers/fsl_sai.c
- common/fsl_drivers/fsl_semc.c
- common/fsl_drivers/fsl_snvs_hp.c
- common/fsl_drivers/fsl_snvs_lp.c
- common/fsl_drivers/fsl_src.c
- common/fsl_drivers/fsl_usdhc.c
- common/fsl_drivers/fsl_wdog.c
- common/fsl_drivers/fsl_qtmr.c
common/startup_mimxrt1052.cpp
common/system_MIMXRT1051.c
drivers/RT1051DriverDMA.cpp
@@ 87,8 57,6 @@ target_include_directories(module-bsp
${CMAKE_CURRENT_SOURCE_DIR}
${CMAKE_CURRENT_SOURCE_DIR}/bsp
${CMAKE_CURRENT_SOURCE_DIR}/common
- ${CMAKE_CURRENT_SOURCE_DIR}/common/fsl_drivers
- ${CMAKE_CURRENT_SOURCE_DIR}/common/cmsis
${CMAKE_SOURCE_DIR}/module-bluetooth/Bluetooth
${CMAKE_SOURCE_DIR}/module-sys/
@@ 102,4 70,7 @@ set_source_files_properties(
target_compile_definitions(module-bsp PUBLIC USB_STACK_FREERTOS)
+add_subdirectory(common/fsl_drivers)
add_subdirectory(${BOARD})
+
+target_link_libraries(module-bsp PUBLIC cmsis fsl)
M module-bsp/board/rt1051/common/chip.hpp => module-bsp/board/rt1051/common/chip.hpp +2 -2
@@ 6,8 6,8 @@
#include <cstdint>
extern "C"
{
-#include "cmsis/cmsis_gcc.h"
-#include "cmsis/core_cm7.h"
+#include "cmsis_gcc.h"
+#include "core_cm7.h"
#include "fsl_drivers/fsl_src.h"
#include "macros.h"
}
A module-bsp/board/rt1051/common/fsl_drivers/CMakeLists.txt => module-bsp/board/rt1051/common/fsl_drivers/CMakeLists.txt +74 -0
@@ 0,0 1,74 @@
+add_library(fsl STATIC)
+
+target_sources(fsl
+ PRIVATE
+ fsl_adc.c
+ fsl_cache.c
+ fsl_clock.c
+ fsl_common.c
+ fsl_dcdc.c
+ fsl_dmamux.c
+ fsl_edma.c
+ fsl_flexram.c
+ fsl_gpc.c
+ fsl_gpio.c
+ fsl_gpt.c
+ fsl_lpi2c.c
+ fsl_lpspi.c
+ fsl_lpspi_edma.c
+ fsl_lpuart.c
+ fsl_lpuart_edma.c
+ fsl_pit.c
+ fsl_pmu.c
+ fsl_pwm.c
+ fsl_qtmr.c
+ fsl_rtwdog.c
+ fsl_sai.c
+ fsl_sai_edma.c
+ fsl_semc.c
+ fsl_snvs_hp.c
+ fsl_snvs_lp.c
+ fsl_src.c
+ fsl_usdhc.c
+ fsl_wdog.c
+
+ PUBLIC
+ fsl_adc.h
+ fsl_cache.h
+ fsl_clock.h
+ fsl_common.h
+ fsl_dcdc.h
+ fsl_device_registers.h
+ fsl_dmamux.h
+ fsl_edma.h
+ fsl_flexram.h
+ fsl_gpc.h
+ fsl_gpio.h
+ fsl_gpt.h
+ fsl_iomuxc.h
+ fsl_lpi2c.h
+ fsl_lpspi_edma.h
+ fsl_lpspi.h
+ fsl_lpuart_edma.h
+ fsl_lpuart.h
+ fsl_pit.h
+ fsl_pmu.h
+ fsl_pwm.h
+ fsl_qtmr.h
+ fsl_rtwdog.h
+ fsl_sai_edma.h
+ fsl_sai.h
+ fsl_semc.h
+ fsl_snvs_hp.h
+ fsl_snvs_lp.h
+ fsl_src.h
+ fsl_usdhc.h
+ fsl_wdog.h
+)
+
+target_include_directories(fsl
+ PUBLIC
+ $<BUILD_INTERFACE:${CMAKE_CURRENT_LIST_DIR}>
+)
+
+target_link_libraries(fsl PUBLIC cmsis)
R module-os/board/rt1051/fsl_device_registers.h => module-bsp/board/rt1051/common/fsl_drivers/fsl_device_registers.h +0 -0
M module-os/CMakeLists.txt => module-os/CMakeLists.txt +1 -1
@@ 79,4 79,4 @@ if((${PROJECT_TARGET} STREQUAL "TARGET_RT1051") AND (${SYSTEM_VIEW_ENABLED}))
target_link_libraries(${PROJECT_NAME} PUBLIC segger::systemview)
endif()
-target_link_libraries(${PROJECT_NAME} PUBLIC module-bsp module-utils)
+target_link_libraries(${PROJECT_NAME} PUBLIC module-utils)
M module-os/board/rt1051/CMakeLists.txt => module-os/board/rt1051/CMakeLists.txt +7 -0
@@ 1,6 1,7 @@
target_sources(
module-os
PRIVATE
+ _exit.c
fsl_tickless_gpt.c
fsl_tickless_systick.c
fsl_runtimestat_gpt.c
@@ 24,5 25,11 @@ target_include_directories(
$<$<NOT:$<BOOL:${SYSTEM_VIEW_ENABLED}>>:
${CMAKE_CURRENT_SOURCE_DIR}
>
+ ${CMAKE_CURRENT_SOURCE_DIR}/include
>
)
+
+target_link_libraries(module-os
+ PUBLIC
+ cmsis
+)
R board/rt1051/_exit.c => module-os/board/rt1051/_exit.c +0 -0
R module-bsp/board/rt1051/common/macros.h => module-os/board/rt1051/include/macros.h +0 -0