~aleteoryx/muditaos

ref: 32c6769cb684b99d6154c41fa72a421ce1e23c0c muditaos/module-bsp/board/rt1051/os/include/macros.h -rw-r--r-- 2.4 KiB
32c6769c — Lefucjusz [BH-1657][BH-1833][BH-1854] Add WFI and SDRAM self-refresh mode 1 year, 11 months ago 
                                                                                
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// Copyright (c) 2017-2023, Mudita Sp. z.o.o. All rights reserved.
// For licensing, see https://github.com/mudita/MuditaOS/LICENSE.md

#pragma once

#include "MIMXRT1051.h"
#include <stdbool.h>
#include <assert.h>

#define _STRINGIFY(s) #s
#define STRINGIFY(s)  _STRINGIFY(s)

#define ALIGN_(n) __attribute__((aligned(n)))

#define CACHEABLE_SECTION_SDRAM(var) __attribute__((section(".sdram"))) var

#define CACHEABLE_SECTION_SDRAM_ALIGN(var, alignbytes)                                                                 \
    __attribute__((section(".sdram"))) __attribute__((aligned(alignbytes))) var

#define NONCACHEABLE_SECTION_SDRAM(var) var

#define NONCACHEABLE_SECTION_SDRAM_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))

#define NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var

#define NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)                                                               \
    __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))

#define NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var

#define NONCACHEABLE_SECTION_ALIGN(var, alignbytes)                                                                    \
    __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))

#define WFI_CODE_SECTION(var) __attribute__((section(".wficode"), noinline)) var

static inline uint32_t IS_MEM_ADDR_CACHED(void *addr)
{
    extern uint32_t __ocram_noncached_start[];
    extern uint32_t __ocram_noncached_end[];
    extern uint32_t __dtcm_ram_start[];
    extern uint32_t __dtcm_ram_end[];
    extern uint32_t __sdram_cached_start[];
    extern uint32_t __sdram_cached_end[];

    if (((uint32_t *)addr >= (uint32_t *)__ocram_noncached_start) &&
        ((uint32_t *)addr < (uint32_t *)__ocram_noncached_end)) {
        return 0;
    }
    if (((uint32_t *)addr >= (uint32_t *)__dtcm_ram_start) && ((uint32_t *)addr < (uint32_t *)__dtcm_ram_end)) {
        return 0;
    }
    if (((uint32_t *)addr >= (uint32_t *)__sdram_cached_start) && ((uint32_t *)addr < (uint32_t *)__sdram_cached_end)) {
        return 1;
    }

    assert(0);
}

//! Test if in interrupt mode
static inline bool isIRQ()
{
    return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0;
}

static inline void haltIfDebugging()
{
    if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) {
        __asm("bkpt 1");
    }
}