Maddie's test ISA Version 1.0


Table of contents:
1 - Overview
2 - Instruction composition
3 - Instruction categories
4 - Instruction descriptions



Overview: -- TODO: clean up for readability
This is a simplistic 16 bit RISC ISA, which describes a largely stateless CPU, the only
statefulness that is described is the ability to toggle interrupts.
There are no described SIMD or floating point capabilities, this will likely change
in future versions of this ISA.
The versioning is delineated such that minor versions are backwards compatible, while major versions are not.
The serial port is primarily designed for interfacing with STDIN/STDOUT in simulated versions,
although it may be useful in hardware also.
Interrupts can either be triggered by software, for the purposes of providing a standard location in memory,
or triggered by hardware, for now this is just for keyboard interrupts.
One major feature is that all instructions have the option to have a condition attached, located in the first
four bits of each instruction, functioning as two toggles and two requirements, in order to facilitate
negative conditons.
This ISA describes a CPU with variable length instructions, a combined program and general purpose RAM,
and a 16 bit word length, with registers to match.
Memory is word addressable, and up to 65535 main memory addresses are available, with up to 2^32 words of
disk space accessible through use of the disk index register.
There are 32 registers, the first of which is reserved for interrupts, software or otherwise.
Upon boot, the first 512 words of disk are copied to main memory.

Instruction categories: